Aspects are related generally to computer-based communication systems, and more specifically to multi-packet processing with enforcement of ordering rules in a computer system.
Peripheral component interconnect express (PCIe) is a component level interconnect standard that defines a bi-directional communication protocol for transactions between input/output (I/O) adapters and host systems. PCIe communications are encapsulated in packets according to the PCIe standard for transmission on a PCIe bus. Packets originating at I/O adapters and ending at host systems are referred to as upbound packets. Packets originating at host systems and terminating at I/O adapters are referred to as downbound packets. PCIe transactions include a request packet and, if required, a completion packet (also referred to herein as a “response packet”) in the opposite direction. The PCIe topology is based on point-to-point unidirectional links that are paired (e.g., one upbound link, one downbound link) to form the PCIe bus.
A high-bandwidth PCIe link (x16) can transmit two full transaction layer packets (TLPs) in a single scaled clock cycle and must process two TLPs in the order received. A PCIe device must perform TLP assembly, decoding, and routing of inbound TLPs. TLPs are typically received in double word (4 byte) multiples which must be assembled to determine how to process them as headers and data payloads of various lengths. TLPs must be processed in the order that they are transmitted. In some PCIe instances, the bandwidth is high enough to cause two full PCIe TLPs to be received in a single cycle. TLPs must be processed without placing back-pressure (e.g., excessive delay) on the link at this rate, and thus, there is a need for a method to assemble and process the TLPs at this rate.